The present invention relates to configuration of logic elements for use with programmable logic devices or other similar devices.
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include one or more look-up tables (LUTs) or product terms, carry-out chains, registers, and other elements. A typical LUT circuit used as a logic element provides an output signal that is a function of multiple input signals. The particular logic function may be determined by programming the LUT's memory elements. Additionally, LEs typically include registers to perform sequential logic functions. However, it is sometimes the case the logic function carried out by an LE does not require a register. As such, registers in LEs may remain unused in a particular configuration, thereby reducing the density of the logic in a configuration.
One such example of a logic function that may be carried out by a PLD is a multiplication of two numbers. Such multiplier configurations can require the configuration of individual single bit multipliers followed by a series of adders. These single bit multipliers and adders are generally configured using the LUTs of a PLD. In such a case, the registers are not typically used for the multiplication function and, thus, may go unused altogether.